Clock and data recovery (CDR) circuits are widely used when a data signal is sent across a communications link without an accompanying dedicated clock signal. CDR circuits typically use a phase-locked loop (PLL) to determine, from the transitions between physical data values, the exact frequency at which data is arriving and the optimum phase at which to sample the incoming data. PLLs typically include a VCO, a frequency detector, and a phase detector. The phase detector is used to determine the optimum phase at which to sample the incoming data. Phase detectors require that the frequency of a VCO be very close to the frequency of the incoming signal before frequency and phase lock can be achieved. For example, the frequencies of the VCO and incoming signal should be within 0.5% of each other before the phase detector is able to “pull-in” the VCO frequency to match the incoming signal. Frequency detectors are designed to bring the frequency of the VCO to within the pull-in range, or deadband region, of the phase detector. Frequency detectors relinquish control of the VCO signal to the phase detector once the VCO frequency has been brought into the deadband region.
PLLs often use “bang-bang” type phase detectors. Bang-bang phase detectors, also referred to as “binary” or “up/down” phase detectors, output an indication of the phase of the incoming signal relative to the VCO signal using an up or down (up/down) signal. The up/down signal has no information on how far the phase of the VCO signal differs from the incoming signal. The pull-in range of a bang-bang phase detector is proportional to the size of the immediate change in VCO frequency that results from an up or down signal. The immediate change in VCO frequency that results from an up/down signal is generally referred to as the “bang-bang step size” or simply the “step size.” PLLs that utilize bang-bang phase detectors are often referred to as bang-bang PLLs.
One problem with PLLs, including bang-bang PLLs, is frequency detector overshoot. Frequency detector overshoot occurs when the frequency detector causes the VCO frequency to oscillate around the deadband region without being able to drive the VCO frequency into the deadband region. This can happen if the deadband region is too narrow. Another common problem with PLLs is charge pump leakage. Charge pump leakage can make the phase detector's pull-in range asymmetrical and can prevent the PLL from locking if the deadband region is approached from the wrong side. A narrower deadband region can remedy this problem, but this may lead to frequency detector overshoot.
Although current bang-bang PLLs work well, there is still a need for bang-bang PLLs that are less susceptible to overshoot and charge pump leakage.